Compact layout rule extraction for latchup prevention in a 0.25-/spl mu/m shallow-trench-isolation silicided bulk CMOS process

Author

Ker, Ming-Dou ; Lo, Wen-Yu ; Tung-Yang Chen ; Tang, Howard ; Chen, Tung-Yang ; Wang, M.-C.

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2001

fDate

28-28 March 2001

Firstpage

267

Lastpage

272

Abstract

An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS ICs is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-/spl mu/m shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS ICs, but still to maintain high enough latchup immunity in bulk CMOS ICs.

Keywords

CMOS integrated circuits; circuit layout CAD; integrated circuit layout; integrated circuit reliability; isolation technology; 0.25 micron; area-efficient compact layout rules; compact layout rule extraction; internal core circuits; internal guard rings; latchup immunity; latchup prevention; layout spacings; shallow-trench-isolation; silicided bulk CMOS process; temperature effect; test patterns; Bonding; CMOS integrated circuits; CMOS process; CMOS technology; Equivalent circuits; Integrated circuit layout; Isolation technology; Laboratories; Silicon on insulator technology; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2001 International Symposium on

Conference_Location

San Jose, CA, USA

Print_ISBN

0-7695-1025-6

Type

conf

DOI

10.1109/ISQED.2001.915241

Filename

915241