DocumentCode :
3024208
Title :
DCE3 - An universal real-time clustering engine
Author :
Wassatsch, Andreas ; Richter, Rainer
Author_Institution :
Semicond. Lab., Max-Planck-Inst. for Phys., Munich, Germany
fYear :
2012
fDate :
20-23 May 2012
Firstpage :
3242
Lastpage :
3245
Abstract :
In this paper we describe an universal algorithm for data clustering on hardware level. By utilization of a software-inspired hardware architecture, the clustering task can be executed by a data clustering engine (DCE) in a pipelined data stream mode with a latency of only one frame. The scalable architecture of the clustering core allows a quick adaption of the engine to the specific needs of the target application. Furthermore, a prototype implementation in a TSMC 65nm low power CMOS process and an outlook on the final design for the Belle II experiment at KEK/Japan will be presented.
Keywords :
CMOS integrated circuits; image processing; integrated circuit design; low-power electronics; pattern clustering; Belle II experiment; DCE3; clustering core; data clustering engine; hardware level; low power CMOS process; pipelined data stream mode; size 65 nm; software inspired hardware architecture; universal real time clustering engine; Algorithm design and analysis; Clustering algorithms; Computer architecture; Data acquisition; Detectors; Engines; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
ISSN :
0271-4302
Print_ISBN :
978-1-4673-0218-0
Type :
conf
DOI :
10.1109/ISCAS.2012.6272015
Filename :
6272015
Link To Document :
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