DocumentCode
3024243
Title
A class of downsampled floating tap DFE architectures with application to serial links
Author
Aziz, Pervez M. ; Kimura, Hiroshi ; Malipatil, Amaresh V. ; Kotagiri, Shiva
Author_Institution
LSI Corp., Plano, TX, USA
fYear
2012
fDate
20-23 May 2012
Firstpage
325
Lastpage
328
Abstract
This paper proposes a class of downsampled floating tap decision feedback equalization (DFE) architectures based on downsampling of the floating tap positions. The architectures offer significant complexity and power reduction compared with a standard floating tap DFE architecture with minimal loss in performance. Simulation results with realistic channel models are used to validate the performance of these architectures.
Keywords
decision feedback equalisers; radio links; DFE architectures; decision feedback equalization; downsampled floating tap positions; realistic channel models; serial links; Channel models; Complexity theory; Decision feedback equalizers; Degradation; Delay; Latches; Standards;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location
Seoul
ISSN
0271-4302
Print_ISBN
978-1-4673-0218-0
Type
conf
DOI
10.1109/ISCAS.2012.6272017
Filename
6272017
Link To Document