DocumentCode
302495
Title
Noise shaping with reduced clock frequency
Author
Birru, Dagnachew
Author_Institution
Digital VLSI Group, Philips Res. Lab., Eindhoven, Netherlands
Volume
3
fYear
1996
fDate
12-15 May 1996
Firstpage
233
Abstract
Recently, there have been activities for making the sampling frequency of digital noise shapers (sigma-delta modulators) less than that of the coarsely quantized sequence by an integer factor. Application domains such as video which require a bit-stream sampling frequency in excess of 200 MHz could benefit from such techniques since the major computation in the noise shaper is done at a lower sampling rate. In this paper, a short overview of the reduced clock frequency sigma-delta modulation techniques is presented
Keywords
circuit noise; sigma-delta modulation; 200 MHz; bit-stream; clock frequency; digital noise shaping; quantized sequence; sampling frequency; sigma-delta modulator; video signal; CMOS logic circuits; CMOS technology; Clocks; Delta-sigma modulation; Digital modulation; Filters; Frequency conversion; Frequency modulation; Noise shaping; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.541523
Filename
541523
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