Capturing all admissible linear regions for fast simulations of piecewise-linear dynamic circuits

The dynamics of PWL circuits are usually investigated by executing many and many expensive time-domain simulations, starting from different initial conditions. This paper proposes a pre-analysis stage to reduce the total simulation time. It consists of finding all admissible linear regions, that is the regions which may be crossed by dynamic trajectories. The natural modes of these linear regions are analyzed and stored. So, the CPU time required by each of the successive time-domain simulations is reduced. Also the required storage is moderate, because few linear regions result to be admissible in the circuits of interest