An ultra high speed architecture for VLSI implementation of hash functions

Author

Sklavos, Nicolas ; Dimitroulakos, G. ; Koufopavlou, O.

Author_Institution

Electr. & Comput. Eng. Dept., Patras Univ., Greece

Volume

3

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

990

Abstract

Today, security is a topic which attacks the great interest of researchers. Many encryption algorithms have been investigated, and developed in the last years. The research community efforts are also centered to the efficient implementation of them, in both software platforms and hardware devices. This work is related to hash functions FPGA implementation. Two different hash functions are studied: RIPEMD-160 and SHA-1. A high speed architecture is proposed for the implementation of both of them in the same hardware module. The proposed system reaches throughput values equal to 1,4 for SHA-1 and 1,6 for RIPEMND-160. The proposed system is compared with other related works in both software and hardware.

Keywords

cryptography; data integrity; field programmable gate arrays; hardware-software codesign; pipeline processing; very high speed integrated circuits; FPGA implementation; RIPEMD-160; SHA-1; VLSI implementation; data integrity; data messages; encryption algorithms; hardware devices; hash functions; modified data processes; pipelined methodology; software platforms; ultrahigh speed architecture; Computer architecture; Computer security; Cryptography; Data security; Field programmable gate arrays; Hardware; Message authentication; Programming; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301675

Filename

1301675