Design optimization platform for synthesizable high speed digital filters using retiming technique

In signal processing applications the time critical sections are iterative and recursive and requires various optimization techniques for performance enhancement. Most of these applications require each iteration to be executed under a specific time constraint associated with the data input rate. Using optimization techniques like retiming, we achieve the desired performance. Digital filters are the most common blocks in signal processing applications and they can be represented by synchronous data-flow graphs (DFGs). Applying retiming techniques on the synchronous data flow graphs results in obtaining high speed digital circuits. Retiming is the process of rearranging the storage elements in the circuit to reduce the cycle time without changing its functionality. In this paper, a single optimization environment is developed for retiming the DSP filter blocks using cutset and clock period minimization techniques. Cutset retiming is specially used for filters designed for single processor systems. An optimized digital filter circuit is obtained after retiming from design optimization environment. Also, the HDL(Hardware Description Language) code of the optimized filter circuit is automatically generated and microarchitectural optimizations like usage of parallel prefix tree adders, supply voltage scaling are done at structural level of the circuit which still enhances the filter design performance.