DocumentCode
302689
Title
Evolvable hardware with development
Author
Kitano, Hiroaki
Author_Institution
Sony Comput. Sci. Lab., Tokyo, Japan
Volume
4
fYear
1996
fDate
12-15 May 1996
Firstpage
33
Abstract
Recent progress in semiconductor technologies enable us to use programmable hardware devices, such as the Field Programmable Gate Array (FPGA). When such devices are combined with evolutionary computing techniques, we can develop hardware capable of evolving its circuit configurations on-the-fly. This is an attractive technology since it simultaneously attains real-time performance and adaptive capability. In this paper, we propose the incorporation of the developmental stage in order to generate a circuit configuration matrix. Using this approach, called the grammar encoding method, we evolve a set of graph rewriting rules, whereas the direct encoding method, a conventional approach, evolves the circuit configuration matrix itself. Our approach allows for non-trivial mapping of genotype and phenotype, as well as structure operation capability. Experimental results demonstrate that our approach consistently outperforms the direct encoding method
Keywords
encoding; field programmable gate arrays; genetic algorithms; grammars; logic CAD; logic design; rewriting systems; FPGA; adaptive capability; circuit configuration matrix generation; developmental stage; evolutionary computing techniques; evolvable hardware; field programmable gate array; grammar encoding method; graph rewriting rules; programmable hardware devices; real-time performance; structure operation capability; Biological cells; Computer science; Convergence; Encoding; Field programmable gate arrays; Hardware; Logic circuits; Robots; Scalability; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.541894
Filename
541894
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