DocumentCode
302709
Title
Speed and power comparison of CMOS wave pipelined systems and low power WTGL
Author
Sridhar, Ramalingam ; Martinez-Smith, Alfonso ; Mcgee, Brian
Author_Institution
Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
Volume
4
fYear
1996
fDate
12-15 May 1996
Firstpage
156
Abstract
CMOS wave pipelining is a technique used in high performance digital system design. This paper compares speed and power performance of various CMOS wave pipelined systems. It also presents a modified wave pipelined transmission gate logic for low-power applications and its associated fine tuning method, resulting in a design style for performance in regard to power, delay, and throughput
Keywords
CMOS logic circuits; integrated circuit design; logic design; pipeline processing; CMOS wave pipelining; delay; design; digital system; low power WTGL; speed; throughput; tuning; wave pipelined transmission gate logic; CMOS logic circuits; Digital systems; Inverters; Libraries; Logic design; Logic gates; MOS devices; MOSFETs; Pipeline processing; Propagation delay;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.541923
Filename
541923
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