Development of an LFSR based test pattern generator for functional logic testing

Author

Islam, Syed Zahidul ; Ali, M.A.M. ; Ali, Md Liakot

Author_Institution

Dept. of Electr. Electron. & Syst. Eng., Univ. Kebangsaan Malaysia, Selangor, Malaysia

Volume

2

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

591

Abstract

This paper presents the development of an LFSR based test pattern generator (TPG) to test the functional logic of combinational and sequential circuits. Primitive polynomial based LFSRs and deterministic testing algorithms are applied simultaneously on the circuit under test (CUT) to detect the fault with minimum test length. Fault simulation was performed on ISCAS´85 and ISCAS´89 benchmark circuits using digital fault simulators FSIM and Tetramax. The proposed technique achieved complete fault coverage with shorter test sequences and required less hardware for its implementation.

Keywords

VLSI; automatic test pattern generation; binary sequences; fault simulation; hardware description languages; integrated circuit testing; logic testing; random sequences; shift registers; IC testing scheme; LFSR based test pattern generator; VHDL code; VLSI; combinational circuits; complete fault coverage; deterministic testing algorithms; fault simulation; functional logic testing; minimum test length; polynomial based LFSR; pseudorandom pattern; redundant faults; sequential circuits; shorter test sequences; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Electrical fault detection; Logic testing; Polynomials; Sequential analysis; Sequential circuits; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301854

Filename

1301854