DocumentCode
3028852
Title
Development of a deep submicrometer embedded SRAM compiler
Author
Wu, Zhongyuan ; Gao, Zhiqiang ; He, Xiangqing
Author_Institution
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Volume
2
fYear
2003
fDate
14-17 Dec. 2003
Firstpage
707
Abstract
A high performance embedded SRAM compiler has been developed using 0.18um standard CMOS process. The compiler is capable of generating various single-port SRAM configurations with a minimum 32 bits and up to a maximum 1M bits. An innovative self-timing strategy, using replica cells and a pulsed-clock control module, has been designed for high speed and power reduction. The software feature and the methodology used for layout generation are also discussed.
Keywords
CMOS memory circuits; SRAM chips; circuit layout CAD; memory architecture; timing; clock matching; embedded SRAM compiler; high performance compiler; high speed; layout generation; memory architecture; power reduction; pulsed-clock control module; replica cells; self-timing strategy; sense amplifier; single-port SRAM configurations; standard CMOS process; CMOS process; Circuits; Clocks; Decoding; Delay; Helium; Memory architecture; Random access memory; Standards development; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on
Print_ISBN
0-7803-8163-7
Type
conf
DOI
10.1109/ICECS.2003.1301883
Filename
1301883
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