DocumentCode
3029286
Title
Characterizing Betweenness Centrality Algorithm on Multi-core Architectures
Author
Tu, Dengbiao ; Tan, Guangming
Author_Institution
Lab. of Comput. Syst. & Archit., Chinese Acad. of Sci., China
fYear
2009
fDate
10-12 Aug. 2009
Firstpage
182
Lastpage
189
Abstract
This paper presents an in-depth analysis of characterization for an irregular application - computing betweenness centrality (BC) - on multicore architectures. BC algorithm is widely used in large scale graph analysis applications, which play an increasingly important role in high performance computing community. Through a joint study of architecture and application, we find that dynamically non-contiguous memory access, unstructured parallelism and low arithmetic intensity in BC program pose an obstacle to an efficient execution on parallel architectures. The experimental results report a comparison between Intel Clovertown and Sun Niagara1 for running such irregular program. Finally, several implications on multicore architecture and programming are proposed.
Keywords
graph theory; microprocessor chips; parallel architectures; Intel Clovertown; Sun Niagara1; betweenness centrality algorithm; high performance computing community; large scale graph analysis; microprocessor chip technology; multicore chip architectures; noncontiguous memory access; parallel architectures; Algorithm design and analysis; Arithmetic; Computer applications; Computer architecture; High performance computing; Large-scale systems; Multicore processing; Parallel architectures; Parallel processing; Performance analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing with Applications, 2009 IEEE International Symposium on
Conference_Location
Chengdu
Print_ISBN
978-0-7695-3747-4
Type
conf
DOI
10.1109/ISPA.2009.18
Filename
5207935
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