DocumentCode :
3029354
Title :
Maximum likelihood timing synchronizers for sampled PSK burst TDMA systems
Author :
Dabak, Anand G. ; Hosur, Srinath
Author_Institution :
DSPS R&D Center, Texas Instrum. Inc., Dallas, TX, USA
Volume :
2
fYear :
1997
fDate :
12-16 Oct 1997
Firstpage :
686
Abstract :
A new maximum-likelihood (ML) symbol timing estimator for sampled, coherent, burst time division multiple access (TDMA), phase shift keyed (PSK) systems is derived. The estimator uses a periodic bit pattern for acquisition. The sufficient statistic turns out to be the ratio of the even and odd sample sums which is easily implementable digitally with much lower complexity as compared to previously proposed ML implementations. The performance of the new estimator is very close to the Cramer-Rao (CR) bound. It outperforms previously proposed sub-optimal estimators by about 2.0 dB and does not suffer from hangups, a common problem in all phase lock loop (PLL) based timing acquisition systems
Keywords :
maximum likelihood estimation; phase shift keying; signal sampling; statistical analysis; synchronisation; time division multiple access; timing; Cramer-Rao bound; ML symbol timing estimator; PLL based timing acquisition systems; acquisition; coherent TDMA systems; even to odd sample sums ratio; maximum likelihood timing synchronizers; performance; periodic bit pattern; phase lock loop; phase shift keyed systems; receiver synchronization; sampled PSK burst TDMA systems; sub-optimal estimators; sufficient statistic; Chromium; Digital signal processing; Matched filters; Maximum likelihood estimation; Phase estimation; Phase locked loops; Phase shift keying; Statistics; Time division multiple access; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Universal Personal Communications Record, 1997. Conference Record., 1997 IEEE 6th International Conference on
Conference_Location :
San Diego, CA
ISSN :
1091-8442
Print_ISBN :
0-7803-3777-8
Type :
conf
DOI :
10.1109/ICUPC.1997.627252
Filename :
627252
Link To Document :
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