A fast and area-efficient VLSI architecture for embedded image coding

Author

Bae, Jongwoo ; Prasanna, Viktor K.

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

Volume

3

fYear

1995

fDate

23-26 Oct 1995

Firstpage

452

Abstract

We propose a VLSI architecture for an embedded zerotree wavelet (EZW) algorithm. Our partitioning and mapping of the computations leads to parallel operations of independent processors and balances the workload. Our data mapping technique simplifies the memory access and the processor architecture. The resulting architecture is area-efficient and can be used to design a low-power system for mobile/visual communication applications. A video codec based on the parallel architecture can simultaneously handle multiple video channels of various resolutions

Keywords

VLSI; digital signal processing chips; image coding; image resolution; land mobile radio; parallel architectures; video codecs; video coding; visual communication; wavelet transforms; VLSI architecture; area efficient architecture; data mapping technique; embedded image coding; embedded zerotree wavelet algorithm; independent processors; low-power system design; memory access; mobile communication applications; multiple video channels; parallel architecture; parallel operations; partitioning; processor architecture; video codec; video resolutions; visual communication applications; Computer architecture; Discrete wavelet transforms; Image coding; Parallel architectures; Partitioning algorithms; Very large scale integration; Video codecs; Video compression; Visual communication; Wavelet coefficients;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing, 1995. Proceedings., International Conference on

Conference_Location

Washington, DC

Print_ISBN

0-8186-7310-9

Type

conf

DOI

10.1109/ICIP.1995.537669

Filename

537669