• DocumentCode
    3029906
  • Title

    The need for usable formal methods in verification and validation

  • Author

    Gore, Rajeev ; Diallo, Saikou

  • Author_Institution
    Virginia Modeling, Anal. & Simulation Center, Old Dominion Univ., Norfolk, VA, USA
  • fYear
    2013
  • fDate
    8-11 Dec. 2013
  • Firstpage
    1257
  • Lastpage
    1268
  • Abstract
    The process of developing, verifying and validating models and simulations should be straightforward. Unfortunately, following conventional development approaches can render a model design that appeared complete and robust into an incomplete, incoherent and invalid simulation during implementation. An alternative approach is for subject matter experts (SMEs) to employ formal methods to describe their models. However, formal methods are rarely used in practice due to their intimidating syntax and semantics rooted in mathematics. In this paper we argue for a new approach to verification and validation that leverages two techniques from computer science: (1) model checking and (2) automated debugging. The proposed vision offers an initial path to replace conventional simulation verification and validation methods with new automated analyses that eventually will be able to yield feedback to SMEs in a familiar language.
  • Keywords
    digital simulation; formal verification; program debugging; SME; automated debugging; computer science; mathematics; model checking; model design; model development; model validation; model verification; subject matter experts; usable formal methods; Analytical models; Computational modeling; Computer science; Debugging; Mathematical model; Predictive models; Syntactics;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Simulation Conference (WSC), 2013 Winter
  • Conference_Location
    Washington, DC
  • Print_ISBN
    978-1-4799-2077-8
  • Type

    conf

  • DOI
    10.1109/WSC.2013.6721513
  • Filename
    6721513