• DocumentCode
    3030146
  • Title

    68040 integer module

  • Author

    Holden, Kirk ; Eisele, Renny ; Kobe, Mike ; Raleigh, James ; Spohrer, Thomas

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • fYear
    1990
  • fDate
    17-19 Sep 1990
  • Firstpage
    183
  • Lastpage
    186
  • Abstract
    The central CPU for the 68040 processor is the integer unit (IU). The IU contains multiple 32-bit data and address paths with heavily pipelined instruction execution control for improved performance. Frequently used instructions and addressing modes have been optimized for single cycle execution. Additionally, independent control for each pipe state yields increased throughput. Implementation of control structures for increased performance is presented, with emphasis on design trade-offs for automated logic synthesis versus full custom, hand crafted circuits. The impact of the integration of test logic on behavioral descriptions and control logic testing strategy are discussed
  • Keywords
    built-in self test; logic testing; microprocessor chips; pipeline processing; 32 bit; 68040 integer module; 68040 processor; addressing modes; automated logic synthesis; behavioral descriptions; control logic testing strategy; design trade-offs; integer unit; motorola 68000 family; pipelined instruction execution control; test logic; throughput; Automatic control; Central Processing Unit; Clocks; Counting circuits; Decoding; Kirk field collapse effect; Logic testing; Microprocessors; Prefetching; Programmable logic arrays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-2079-X
  • Type

    conf

  • DOI
    10.1109/ICCD.1990.130197
  • Filename
    130197