An edge based netlist extractor for IC layouts

Author

Aranake, Sandeep ; Dikshit, Anil ; Arun, A.

Author_Institution

Semicond. Complex Ltd., Panjab, India

fYear

1990

fDate

17-19 Sep 1990

Firstpage

195

Lastpage

200

Abstract

An edge-based netlist extractor using a relocatable netlist representation scheme is described. Retaining an existing layout hierarchy, it extracts the devices formed as a result of cell overlaps. Using the implemented overlap-handling algorithm, it is possible to access cell pins not available at the boundary of the cell. The extractor handles all angled geometrics. Total volume of data handled by the extractor is reduced by extracting a cell netlist only only and modifying this netlist according to the nature of the cell instance overlap. The extractor is implemented in C under a Unix environment

Keywords

circuit layout CAD; monolithic integrated circuits; IC layouts; angled geometrics; cell instance overlap; cell overlaps; cell pins; edge based netlist extractor; layout hierarchy; overlap-handling algorithm; relocatable netlist representation; Application specific integrated circuits; Data handling; Data mining; Geometry; Integrated circuit interconnections; Integrated circuit layout; Joining processes; Organizing; Pins; Synthetic aperture sonar;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2079-X

Type

conf

DOI

10.1109/ICCD.1990.130201

Filename

130201