Testability driven synthesis of interacting finite state machines

Sequential testability aspects in the decomposition of finite state machines (FSMs) are addressed. It is shown that the sequential testability of an FSM can be enhanced more easily when the machine is recognized to be, or is synthesized as, an interconnection of smaller machines. An exhaustive classification of redundant faults that can occur in a single FSM embedded in an interacting sequential circuit is presented. Associating each class of these redundant faults with a don´t care set, a synthesis procedure is described that exploits the don´t cares optimally to obtain an irredundant interacting sequential circuit with no area overhead. The synthesis procedure operates on a distributed-style representation of interacting state transition graphs (STGs), carrying out a series of local analyses. Insights into sequential logic synthesis improving on current optimization techniques for interacting sequential circuits are presented