Title :
Heuristic minimization of Boolean relations using testing techniques
Author :
Ghosh, Abhijit ; Devadas, Srinivas ; Newton, A. Richard
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
Minimization of Boolean relations is important from the point of view of synthesis, especially in synthesis for testability. A very fast heuristic procedure for finding an optimal sum-of-products representation for a Boolean relation is described. Starting with a function compatible with the relation, a process of iterative logic improvement based on test generation techniques is used to derive a minimal function compatible with the Boolean relation
Keywords :
Boolean functions; heuristic programming; logic design; logic testing; minimisation of switching nets; Boolean relations; heuristic minimisation; iterative logic improvement; optimal sum-of-products representation; synthesis for testability; test generation techniques; testing techniques; Automata; Boolean functions; Circuit testing; Computer science; Cost function; Feeds; Logic functions; Logic testing; Minimization methods; Programmable logic arrays;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
DOI :
10.1109/ICCD.1990.130226
