Reliability evaluation of FUSS and other reconfiguration schemes

Author

Lopez-Benitez, Noe ; Chean, Mengly

Author_Institution

Dept. of Electr. Eng., Louisiana Tech. Univ., Ruston, LA, USA

fYear

1991

fDate

18-20 Nov 1991

Firstpage

153

Lastpage

156

Abstract

One objective in the design of VLSI/WSI fault-tolerant processor arrays (FTPA), is to increase the probability of successful reconfiguration in the presence of one or more faults given that a fault has occurred (survivability). This paper reports a comparison of FUSS (Full-Use-of-Suitable-Spares), a recently proposed reconfiguration scheme, with other two well reconfiguration schemes. The results reported were obtained using MGRE (Model Generator and Reliability Evaluator). The models generated, already take into account the survivability rate of each reconfiguration scheme. This factor is obtained via simulation or whenever possible analytical expressions are derived

Keywords

VLSI; fault tolerant computing; microprocessor chips; parallel architectures; FUSS; Full-Use-of-Suitable-Spares; Model Generator; Reliability Evaluator; VLSI; WSI; fault-tolerant processor arrays; reconfiguration schemes; reliability evaluation; survivability; Aggregates; Fault tolerance; Fault tolerant systems; Multiplexing; Petri nets; Predictive models; Registers; State-space methods; Stochastic processes; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on

Conference_Location

Hidden Valley, PA

ISSN

1550-5774

Print_ISBN

0-8186-2457-4

Type

conf

DOI

10.1109/DFTVS.1991.199956

Filename

199956