A Reconfigurable Direct RF Receiver With Jitter Analysis and Applications

In typical direct radio frequency (RF) sampling receivers, the sample clock jitter results in SNR degradation on received signals that increases log linearly with RF signal frequency. De-jittering received signals is computationally expensive, especially for wideband communications signals, because the induced jitter on received signals varies as a function of RF signal frequency. This paper considers a reconfigurable direct RF receiver (RDRFR) that has a stair-step jitter pattern as a function of RF signal frequency. The RDRFR uses a two-stage sampling circuit. In the first stage, the RF input is bandpass filtered and pulse sampled without quantizing the signal. The discrete-time analog signal is then interpolated with a continuous time low-pass filter, then sampled and quantized by a traditional analog-to-digital converter. With this two-stage sampling circuit, the induced signal jitter from the RF sampling is identical for all in-band signals and is the same to within an integer scale factor for all signals, in-band or out-of-band. This key circuit property means that it is possible to remove jitter with very low computational complexity in the RDRFR. Furthermore, this result can be exploited to improve system performance with non-ideal anti-alias filters by identifying non-desired signals caused by out-of-band leakage.