A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond

Author

Bronner, G. ; Aochi, H. ; Gall, M. ; Gambino, J. ; Gernhardt, S. ; Hammerl, E. ; Ho, H. ; Iba, J. ; Ishiuchi, H. ; Jaso, M. ; Kleinhenz, R. ; Mii, T. ; Narita, M. ; Nesbit, L. ; Neumueller, W. ; Nitayama, A. ; Ohiwa, T. ; Parke, S. ; Ryan, J. ; Sato, T. ;

Author_Institution

IBM Corp., Hopewell Junction, NY, USA

fYear

1995

fDate

6-8 June 1995

Firstpage

15

Lastpage

16

Abstract

Results are presented for a fully planarized 0.25 /spl mu/m technology using a trench storage capacitor known as the "BEST" cell. In order to achieve a wide process window for fine patterning, a comprehensive global planarization scheme utilizing chemical mechanical polishing (CMP) is employed. This scheme permits two levels of wiring at a minimum contacted pitch of 0.55 /spl mu/m and allows simplification of other processes related to the gate electrode and borderless array bitline contact. The technology has been exercised to fabricate a 256 Mb DRAM and is extendable to the 1 Gb generation by incremental technology scaling.

Keywords

CMOS memory circuits; DRAM chips; etching; integrated circuit technology; polishing; 0.25 micron; 0.55 micron; 256 Mbit; CMP; DRAM; borderless array bitline contact; chemical mechanical polishing; dynamic RAM; fully planarized CMOS technology; global planarization scheme; incremental technology scaling; submicron process; trench storage capacitor; Aluminum; CMOS technology; Capacitors; Chemical technology; Electrodes; Focusing; Lithography; Planarization; Random access memory; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

0-7803-2602-4

Type

conf

DOI

10.1109/VLSIT.1995.520837

Filename

520837