DocumentCode
3033686
Title
Radiation hardness-by-design SRAM design for 0.15µm fully depleted SOI-ASIC
Author
Makihara, A. ; Yokose, T. ; Tsuchiya, Y. ; Miyazaki, Y. ; Ebihara, T. ; Maru, A. ; Shindou, H. ; Kuboyama, S.
Author_Institution
High-Reliability Eng. & Components Corp., Tsukuba, Japan
fYear
2011
fDate
19-23 Sept. 2011
Firstpage
164
Lastpage
168
Abstract
This paper describes the Single Event Effect test result on the Radiation Hardness-By-Design SRAM for 0.15μm Fully Depleted CMOS/SOI-ASIC fabricated by a commercial foundry. Sufficient immunity was demonstrated for the SEU/SET required for space applications.
Keywords
CMOS memory circuits; SRAM chips; application specific integrated circuits; integrated circuit design; radiation hardening (electronics); silicon-on-insulator; SEU-SET; fully depleted CMOS-SOI-ASIC; fully depleted SOI-ASIC; radiation hardness-by-design SRAM design; single event effect test; size 0.15 mum; Inverters; Logic gates; Radiation effects; Random access memory; Single event upset; Transistors; 0.15µm Fully Depleted CMOS/SOI; ASIC; Radiation Hardness-By-Design; SRAM; Single Event Effects; commercial foundry;
fLanguage
English
Publisher
ieee
Conference_Titel
Radiation and Its Effects on Components and Systems (RADECS), 2011 12th European Conference on
Conference_Location
Sevilla
ISSN
0379-6566
Print_ISBN
978-1-4577-0585-4
Type
conf
DOI
10.1109/RADECS.2011.6131391
Filename
6131391
Link To Document