Emitter Pedestal Design of GaInP/GaAs Heterojunction Bipolar Transistors

Author

Lopez-González, Juan M.

Author_Institution

Univ. Politecnica de Catalunya, Barcelona

fYear

2007

fDate

Jan. 31 2007-Feb. 2 2007

Firstpage

348

Lastpage

350

Abstract

This paper shows some consequences of the design of the emitter pedestal in the electric DC and AC performance of GalnP/GaAs Heterojunction Bipolar Transistors. Two HBT transistors are compared which have the same wafer area and base and collector contact areas, and very similar cutoff frequency and maximum frequency, approximately 80 and 40 GHz. The results show that it is possible to optimize the heterojunction bipolar transistor design keeping the MMIC rules and the wafer area utilized.

Keywords

III-V semiconductors; MMIC; gallium arsenide; gallium compounds; heterojunction bipolar transistors; millimetre wave bipolar transistors; GaInAs-GaAs; MMIC rules; emitter pedestal design; frequency 40 GHz; frequency 80 GHz; gallium compounds; heterojunction bipolar transistors; indium compounds; Analytical models; Bipolar transistors; Cutoff frequency; Design engineering; Design optimization; Doping profiles; Gallium arsenide; Heterojunction bipolar transistors; MMICs; Threshold voltage; Gallium compounds; Heterojunction bipolar transistors; Semiconductor device modeling; Semiconductor heterojunctions;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices, 2007 Spanish Conference on

Conference_Location

Madrid

Print_ISBN

1-4244-0868-7

Type

conf

DOI

10.1109/SCED.2007.384065

Filename

4271243