DocumentCode :
3034174
Title :
A symmetric 0.25 /spl mu/m CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithography
Author :
Boulin, D.M. ; Mansfield, W.M. ; O´Connor, K.J. ; Bevk, J. ; Brasen, D. ; Cheng, M. ; Cirelli, R.A. ; Eshraghi, S.A. ; Green, M.L. ; Guinn, K.V. ; Hillenius, S.J. ; Ibbotson, D.E. ; Jacobson, D.C. ; Kim, Y.O. ; King, C.A. ; Kistler, R.C. ; Klemens, F.P. ;
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
fYear :
1995
fDate :
6-8 June 1995
Firstpage :
65
Lastpage :
66
Abstract :
A 0.25 /spl mu/m coded feature CMOS technology has been developed for high-performance, low-power ASIC applications. Critical process features include 248 nm DUV lithography on all levels, profiled twin tubs by high energy implantation (HEI), dual TiN/polysilicon gates with low resistance on minimum size lines, rapid thermal (RT) N/sub 2/O grown 5.5 nm gate dielectrics, and planarized multi-level interconnect. Transistors are demonstrated with symmetric thresholds and excellent short-channel characteristics down to channel lengths of 0.18 /spl mu/m. Fabricated circuits operate down to <1 V supplies, with <20 ps ring oscillator gate delays achieved for 0.2 /spl mu/m gate devices, a record for stepper-based lithography with conventional resist processing.
Keywords :
CMOS integrated circuits; application specific integrated circuits; integrated circuit technology; photolithography; 0.25 micron; 1 V; 248 nm; DUV lithography; circuit fabrication; dual TiN/polysilicon gates; gate dielectrics; high energy implantation; low-power ASICs; planarized multi-level interconnects; rapid thermal processing; resist processing; resistance; ring oscillator gate delays; short-channel characteristics; stepper; symmetric CMOS technology; thresholds; transistors; twin tubs; Application specific integrated circuits; CMOS technology; Delay; Dielectrics; Integrated circuit interconnections; Lithography; Rapid thermal processing; Ring oscillators; Thermal resistance; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7803-2602-4
Type :
conf
DOI :
10.1109/VLSIT.1995.520860
Filename :
520860
Link To Document :
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