Testbench components verification using fault injection techniques

New methodologies for digital designs verification make use of SystemVerilog´s object-oriented mechanisms to speed-up the verification environment development. Yet, undetected testbench errors can slow down or even compromise the overall verification process. This paper concentrates on fault injection technique applied to different SystemVerilog testbench components. By altering functionality in different places of the testbench, potential hidden errors can be detected, improving the testbench capacity to detect design misbehavior. The fault injection in SystemVerilog testbench components may be used in addition to existing methods of functional verification analysis, for testbench validation. Modalities to alter the main testbench components are presented, highlighting the effects on the testbench behavior.