Minimization of multioutput TANT networks for unlimited fan-in network model

Author

Perkowski, Marek A. ; Chrzanowska-Jeske, Malgorzata ; Shah, Tushar

Author_Institution

Dept. of Electr. Eng., Portland State Univ., OR, USA

fYear

1990

fDate

17-19 Sep 1990

Firstpage

360

Lastpage

363

Abstract

A program for the minimization of multi-output three-level Boolean networks from NAND gates of unlimited fan-in is described. This model includes don´t care states. The algorithm is fast and creates good-quality approximate solutions, and its efficiency increases with the percentage of don´t cares. It has been tried on about 40 Boolean functions of not more than 14 inputs, and yielded correct results. The realized circuits (on PLH501 and PLH502 PLDs) required up to 68% (on the average 35%) less gates than the corresponding PLAs. The program can consider tradeoffs between the solution-cost and the processing speed by using various type of the source data

Keywords

Boolean functions; minimisation of switching nets; Boolean functions; NAND foldback architecture; NAND gates; PLH501; PLH502; TANT-PLD program; don´t care states; minimization; multi-output three-level Boolean networks; multioutput TANT networks; processing speed; solution-cost; unlimited fan-in network model; Boolean functions; Delay; Input variables; Logic circuits; Logic design; Logic devices; Logic functions; Minimization; Programmable logic arrays; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2079-X

Type

conf

DOI

10.1109/ICCD.1990.130254

Filename

130254