Performance limits of superlattice-based steep-slope nanowire FETs

Author

Gnani, E. ; Maiorano, P. ; Reggiani, S. ; Gnudi, A. ; Baccarani, G.

Author_Institution

Dept. of Electron., Univ. of Bologna, Bologna, Italy

fYear

2011

fDate

5-7 Dec. 2011

Abstract

In this work we investigate the achievable device performance of steep-slope nanowire FETs based on the filtering of the high-energy electrons via a superlattice heterostructure in the source extension. Four material pairs are investigated for the superlattice (SL), with the aim to identify the most promising ones with respect to the typical FET evaluation metrics. We found that the InGaAs-InAlAs pair can provide an inverse subthreshold slope SS = 13 mV/dec and an on-state current I_ON = 4.5 mA/μm@V_DD = 0.4V. These results outperform the ITRS requirements for the 21 nm technology node.

Keywords

III-V semiconductors; aluminium compounds; field effect transistors; gallium arsenide; indium compounds; nanoelectronics; nanowires; semiconductor superlattices; FET evaluation metrics; InGaAs-InAlAs; high-energy electron filtering; inverse subthreshold slope; size 21 nm; superlattice heterostructure; superlattice-based steep-slope nanowire FET; voltage 0.4 V; Electric potential; FETs; Logic gates; Optimization; Superlattices; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2011 IEEE International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

978-1-4577-0506-9

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2011.6131491

Filename

6131491