Structural effects on Chip Package Interaction and mechanical reliability of Cu/low-k multi-layer interconnects in flip-chip package

Author

Lee, Michael G. ; Uchibori, Chihiro J.

Author_Institution

Fujitsu Labs. of America, Inc., Sunnyvale, CA, USA

fYear

2010

fDate

6-9 June 2010

Firstpage

1

Lastpage

3

Abstract

The effects of structural design on the mechanical reliability of Cu/low-k multi-layer interconnects are investigated using finite element method. The Chip Package Interaction (CPI) was analyzed for a model of twelve wiring layers to calculate the energy release rate (ERR). The relations between the feature dimensions, such as copper interconnect width and low-k dielectric thickness, and the interfacial fracture are studied. Also, implications on the design rules for interconnect and reliability are discussed.

Keywords

copper; finite element analysis; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; low-k dielectric thin films; Cu; chip package interaction; energy release rate; flip-chip package; interfacial fracture; low-k dielectric thickness; low-k multi-layer interconnects; mechanical reliability; way finite element method; Copper; Delamination; Dielectric materials; Environmentally friendly manufacturing techniques; Finite element methods; Lead; Plastic packaging; Temperature; Thermal stresses; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2010 International

Conference_Location

Burlingame, CA

Print_ISBN

978-1-4244-7676-3

Type

conf

DOI

10.1109/IITC.2010.5510583

Filename

5510583