Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories

Author

Masoero, L. ; Molas, G. ; Brun, Francesco ; Gely, M. ; Colonna, J.P. ; Della Marca, V. ; Cueto, O. ; Nowak, E. ; De Luca, A. ; Brianceau, P. ; Charpin, C. ; Kies, R. ; Toffoli, A. ; Lafond, D. ; Delaye, V. ; Aussenac, F. ; Carabasse, C. ; Pauliac, Sebasti

Author_Institution

Leti, CEA, Grenoble, France

fYear

2011

fDate

5-7 Dec. 2011

Abstract

In this work, split-gate charge trap memories with electrical gate length down to 20 nm are presented for the 1^st time. Silicon nanocristals (Si-ncs), or silicon nitride (Si₃N₄) and hybrid Sinc/SiN based split-gate memories, with SiO₂ or Al₂O₃ control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. The results are analyzed by means of TCAD simulations.

Keywords

aluminium compounds; elemental semiconductors; embedded systems; flash memories; nanostructured materials; silicon; silicon compounds; technology CAD (electronics); Si-Si₃N₄-Al₂O₃; Si-Si₃N₄-SiO₂; TCAD simulation; electrical gate length; hybrid Si-nanocrystal-SiN based split-gate memory; low-power embedded memory; memory window; silicon nanocrystal; silicon nitride; size 20 nm; split-gate charge trap memory; Charge carrier processes; Dielectrics; Electric fields; Logic gates; Programming; Silicon compounds; Split gate flash memory cells;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2011 IEEE International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

978-1-4577-0506-9

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2011.6131522

Filename

6131522