Sub 0.1 /spl mu/m nMOSFETs fabricated using experimental design techniques to optimise performance and minimise process sensitivity

Author

Kubicek, S. ; Biesemans, S. ; Wang, Q.F. ; Maex, K. ; De Meyer, K.

Author_Institution

IMEC, Leuven, Belgium

fYear

1995

fDate

6-8 June 1995

Firstpage

105

Lastpage

106

Abstract

Bulk nMOS transistors with nominal poly length of 0.12 /spl mu/m and minimum effective channel length below 0.1 /spl mu/m were fabricated. Arsenic S/D shallow extensions and optimised channel doping by Indium were used to suppress the short channel effect (SCE) as well as the reverse-SCE. E-beam lithography was used for poly level definition and an advanced Co/Ti salicidation scheme was applied to reduce the sheet resistance to below 4 /spl Omega//square for poly widths down to 0.08 /spl mu/m. Design of Experiments (DOE) was used in defining the lot splits to study the influence of technological parameters on the device performance and its sensitivity to fluctuations in process parameters.

Keywords

MOSFET; design of experiments; semiconductor technology; 0.1 micron; Co/Ti salicidation; E-beam lithography; arsenic S/D shallow extension; experimental design; fabrication; indium channel doping; nMOSFETs; performance optimisation; poly level definition; process sensitivity; reverse-SCE; sheet resistance; short channel effect; Boron; Conductivity; Design for experiments; Design optimization; Indium; Isolation technology; Lithography; MOSFETs; Resists; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

0-7803-2602-4

Type

conf

DOI

10.1109/VLSIT.1995.520879

Filename

520879