• DocumentCode
    3038282
  • Title

    Defect Tolerance for a Capacitance Based Nanoscale Biosensor

  • Author

    Chapman, Glenn H. ; Jain, Vijay K.

  • Author_Institution
    Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC
  • fYear
    2008
  • fDate
    1-3 Oct. 2008
  • Firstpage
    220
  • Lastpage
    228
  • Abstract
    A capacitance based nanoscale biosensor and its defect tolerance are explored. The sensor consists of a microchamber that can be filled with the fluid under test. In a two step procedure the capacitance is measured between the upper plate and the lower plate first for (a) benign fluid, and then for (b) the test fluid, potentially containing the antigens. In each of these tests, an on-chip oscillator provides a test signal of selectable frequency. As shown in the paper the output signal can be processed by on-chip digital modules to estimate the capacitance values. A decision is then made not only on the presence/absence of the antigens, but also on the level of concentration in the medium. We describe the fabrication steps for the sensor plane, the 3-D architecture and the detection methodology, efficient circuits on the analog plane, and the J-platform on the digital plane. However, due the confluence of diverse technologies involved, the probability of defects is higher than that encountered in the usual 2-D device. Therefore, we propose defect tolerance for the planes of this 3-D biosensor. For example, on the sensor plane multiple chambers for the test fluid of defect resistant design are provided, rather than just one, and their measurements used for reliable estimates.
  • Keywords
    biosensors; capacitive sensors; lab-on-a-chip; defect tolerance; microchamber; nanoscale biosensor; Biosensors; Capacitance measurement; Circuits; Fabrication; Frequency; Immune system; Oscillators; Sensor phenomena and characterization; Signal processing; Testing; 3-D SoC; Biosensor; J-platform; analog circuits; antigen; digital VLSI cells; diseased cell detection; nanoscale;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on
  • Conference_Location
    Boston, MA
  • ISSN
    1550-5774
  • Print_ISBN
    978-0-7695-3365-0
  • Type

    conf

  • DOI
    10.1109/DFT.2008.45
  • Filename
    4641176