Systematic understanding of self-heating effects in tri-gate nanowire MOSFETs considering device geometry and carrier transport

Self-heating effects (SHE) in nanowire transistors (NW Tr.) have been systematically studied with respect to the dependence on the NW width (W), NW height (H), and gate length (L_g). Temperature rise (ΔT) by SHE in NW Tr. is smaller than SOI planar Tr. when compared with power consumption per unit area. Instead, ΔT at the same total power consumption (not normalized by area) is independent of W, H and L_g in sub-100nm regions, since the heated area does not scale with L_g and W. Drain current (I_d) reduction by SHE is almost constant for a wide range of L_g due to the weak temperature dependence of I_d in velocity saturation regime. I_d reduction in narrow NW Tr. is slightly less than that in wide NW Tr. because of the stronger velocity saturation at the same power consumption.