ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction

Author

Remersaro, Santiago ; Rajski, Janusz ; Rinderknecht, Thomas ; Reddy, Sudhakar M. ; Pomeranz, Irith

Author_Institution

ECE Dept., Univ. of Iowa, Iowa City, IA

fYear

2008

fDate

1-3 Oct. 2008

Firstpage

385

Lastpage

393

Abstract

As digital circuits grow in gate count so does the data volume required for manufacturing test. To address this problem several test compression techniques have been developed. This paper presents a novel and scalable technique for inserting observation points to aid compression by reducing pattern count and data volume. Experimental results presented for industrial circuits demonstrate the effectiveness of the method.

Keywords

automatic test pattern generation; integrated circuit testing; logic testing; data volume reduction; digital circuits; enhanced compaction; heuristics dependant observation point insertion; industrial circuits; manufacturing test; test compression techniques; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Controllability; Electrical fault detection; Fault detection; Logic testing; ATPG; compact test sets; test compression; test point insertion;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on

Conference_Location

Boston, MA

ISSN

1550-5774

Print_ISBN

978-0-7695-3365-0

Type

conf

DOI

10.1109/DFT.2008.39

Filename

4641195