Title :
Designing a memory module tester
Author :
Van der Velde, Daniël P. ; Goor, A. J V D
Author_Institution :
Dept. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
Abstract :
In the manufacturing process of memory modules (such as SIMMs and DIMMs), first memories are tested at the die level, then at the chip level, and finally at the module level. For the latter special module testers are available. This paper gives an analysis of commercially available module testers and shows their restrictions. Then it lists the requirements for a more advanced module tester, after which a complete functional design is given. The result is a very flexible tester capable of testing FPM/EDO and SDRAM memories, programmable using Texas Instruments TMS320C6201 DSPs and Vantis CPLDs, with an expected end-user price of less than US$ 20,000
Keywords :
DRAM chips; integrated circuit testing; modules; timing; DIMMs; FPM/EDO memories; SDRAM memories; SIMMs; Texas Instruments TMS320C6201 DSPs; Vantis CPLDs; address scrambling; chip level testing; die level testing; flexible tester; functional design; manufacturing process; memory module tester design; module level testing; programmable tester; timing resolution; topological inversion; Testing;
Conference_Titel :
Memory Technology, Design and Testing, 1999. Records of the 1999 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-0259-8
DOI :
10.1109/MTDT.1999.782689
