• DocumentCode
    3039187
  • Title

    Reducing Power through Compiler-Directed Barrier Synchronization Elimination

  • Author

    Kandemir, Mahmut ; Son, Seung Woo

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
  • fYear
    2006
  • fDate
    4-6 Oct. 2006
  • Firstpage
    354
  • Lastpage
    357
  • Abstract
    Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, many parallelizing compilers are very conservative in inserting barrier synchronizations at the end of each and every parallel loop. This can lead to significant power consumption in chip multiprocessor based execution environments. This paper proposes a compiler-directed approach for eliminating such synchronization calls between neighboring parallel loops. It achieves its goal by partitioning loop iterations across processors such that each processor executes iterations from both the loops that access the same set of array elements. We implemented the proposed approach using an experimental compilation framework and made experiments with ten SPEC benchmark codes. Our experiments clearly show that the proposed compiler-directed approach is very effective and reduces energy overheads due to synchronizations by about 75.5%, and this corresponds to around 5.48% saving on average in overall energy consumption
  • Keywords
    integrated circuit design; low-power electronics; microprocessor chips; multiprocessing systems; parallelising compilers; power consumption; power overhead lines; synchronisation; SPEC benchmark codes; barrier synchronization elimination; compiler-directed approach; interprocessor synchronization; low power design; multiprocessor chip; parallelizing compilers; partitioning loop iterations; performance overheads; power consumption; power overheads; power reduction; Algorithm design and analysis; Computer languages; Computer science; Concurrent computing; Energy consumption; Lead; Parallel processing; Permission; Power engineering and energy; Upper bound; Algorithms; Barrier Elimination; Compiler; Design; Experimentation; Low Power; Performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on
  • Conference_Location
    Tegernsee
  • Print_ISBN
    1-59593-462-6
  • Type

    conf

  • DOI
    10.1109/LPE.2006.4271865
  • Filename
    4271865