Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low-power applications

Author

Fujita, K. ; Torii, Y. ; Hori, M. ; Oh, J. ; Shifren, L. ; Ranade, P. ; Nakagawa, M. ; Okabe, K. ; Miyake, T. ; Ohkoshi, K. ; Kuramae, M. ; Mori, T. ; Tsuruta, T. ; Thompson, S. ; Ema, T.

Author_Institution

Fujitsu Semicond. Ltd., Kuwana, Japan

fYear

2011

fDate

5-7 Dec. 2011

Abstract

We have achieved aggressive reduction of V_T variation and V_DD-min by a sophisticated planar bulk MOSFET named `Deeply Depleted Channel ™ (DDC)´. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing. The 2x reduction of V_T variation in 65nm-node has been demonstrated by matching SRAM pair transistors, 2x improvement in SRAM static noise margin (SNM) and 300 mV V_DD-min reduction of 576Kb SRAM macros to 0.425 V using conventional 6T cell layout.

Keywords

CMOS integrated circuits; MOSFET; SRAM chips; low-power electronics; CMOS platform; SRAM pair transistor; aggressive reduction; cell layout; channel engineering; deeply depleted channel transistor; layered channel formation; low temperature processing; memory size 576 KByte; planar bulk MOSFET; size 65 nm; static noise margin; ultra-low-power application; voltage 0.425 V; voltage 300 mV; Fluctuations; Logic gates; MOS devices; MOSFET circuits; Random access memory; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2011 IEEE International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

978-1-4577-0506-9

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2011.6131657

Filename

6131657