A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAMs of 16 Mbit and beyond

Author

Hayashi, F. ; Kitakata, M.

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1992

fDate

2-4 June 1992

Firstpage

36

Lastpage

37

Abstract

A 0.4- mu m polysilicon TFT with I/sub on/ of 5 mu A and I/sub off/ of 10 fA developed by use of the LDO (lightly doped offset) structure and RTA (rapid thermal annealing) and plasma hydrogenation treatment is discussed. These technologies have proved to be essential in realizing high-performance deep submicron TFTs. Highly stable and low-power SRAMs of 16 Mb and beyond can be realized by employing these technologies. Models and mechanisms to explain the effects of various treatments on the performances of the TFTs are proposed.<>

Keywords

MOS integrated circuits; SRAM chips; VLSI; annealing; hydrogen; integrated circuit technology; rapid thermal processing; thin film transistors; 0.4 micron; 10 fA; 16 Mbit; 5 muA; LDO; RTA; SRAMs; VLSI; deep submicron TFTs; lightly doped offset; plasma hydrogenation; polycrystalline Si:H; polysilicon TFT; rapid thermal annealing; Annealing; Crystallization; National electric code; Plasma immersion ion implantation; Plasma stability; Random access memory; Strontium; Thin film transistors; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0698-8

Type

conf

DOI

10.1109/VLSIT.1992.200634

Filename

200634