DocumentCode
3042131
Title
A functional test generation technique for RTL datapaths
Author
Alizadeh, Behrooz ; Fujita, Masayuki
Author_Institution
Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran
fYear
2012
fDate
9-10 Nov. 2012
Firstpage
64
Lastpage
70
Abstract
This paper presents an automatic test pattern generation (ATPG) technique applicable to register transfer level (RTL) datapath circuits which are usually very hard-to-test due to the presence of complex loop structures. Although to achieve high fault coverage it is essential to symbolically simulate all possible execution paths, we have come up with a case splitting mechanism which makes use of path sensitization information from the faulty location to primary outputs so that the size of formulae to be solved is significantly reduced. Experimental results show robustness and reliability of our method compared to the state-of-the-art RTL ATPG techniques. In addition, the results indicate that, in comparison with [8], with case splitting the ATPG time has been reduced by 22%-41%.
Keywords
automatic test pattern generation; integrated circuit reliability; integrated circuit testing; RTL datapath circuits; automatic test pattern generation; case splitting; complex loop structures; execution paths; fault coverage; functional test generation; path sensitization information; register transfer level; reliability; Automatic test pattern generation; Circuit faults; Educational institutions; Integrated circuit modeling; Polynomials; Sequential circuits; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
High Level Design Validation and Test Workshop (HLDVT), 2012 IEEE International
Conference_Location
Huntington Beach, CA
ISSN
1552-6674
Print_ISBN
978-1-4673-2897-5
Type
conf
DOI
10.1109/HLDVT.2012.6418244
Filename
6418244
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