DocumentCode :
3042449
Title :
An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles
Author :
Mondal, Md Nazrul Islam ; Nakano, Koji ; Ito, Yasuaki
Author_Institution :
Dept. of Inf. Eng., Hiroshima Univ., Higashi-Hiroshima, Japan
fYear :
2011
fDate :
Nov. 30 2011-Dec. 2 2011
Firstpage :
77
Lastpage :
86
Abstract :
Field Programmable Gate Arrays (FPGAs) are a dominant implementation medium for digital circuits which are used to embed a circuit designed by users instantly. FPGAs can be used for implementing parallel and hardware algorithms. Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert the circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs.
Keywords :
asynchronous circuits; equivalent circuits; field programmable gate arrays; read-only storage; asynchronous ROM; equivalent circuit; field programmable gate array; read only memory; Clocks; Combinational circuits; Field programmable gate arrays; Random access memory; Read only memory; Registers; Synchronization; Asynchronous read operations; Circuit rewriting algorithm; FPGA; Read only memories;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Networking and Computing (ICNC), 2011 Second International Conference on
Conference_Location :
Osaka
Print_ISBN :
978-1-4577-1796-3
Type :
conf
DOI :
10.1109/ICNC.2011.20
Filename :
6131796
Link To Document :
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