DocumentCode
3043556
Title
Composability in the time-triggered system-on-chip architecture
Author
Kopetz, H. ; El Salloum, C. ; Huber, B. ; Obermaisser, R. ; Paukovits, C.
Author_Institution
Inst. of Comput. Eng., Vienna Univ. of Technol., Vienna
fYear
2008
fDate
17-20 Sept. 2008
Firstpage
87
Lastpage
90
Abstract
The composition of a large SoC out of pre-validated IP-cores requires an architecture that enables the seamless integration of components, i.e. composability. In this paper we present the five principles of composability that must be supported by any architecture that claims to enable the constructive composition of components. After the introduction of the TTSoC architecture and a description of a prototype implementation we show how this architecture conforms to the principles of composability.
Keywords
system-on-chip; IP-cores; SoC compasability; TTSoC architecture; principles of composability; time-triggered system-on-chip architecture; Computer architecture; Cryptography; Electrical equipment industry; Encoding; Hardware; Network-on-a-chip; Protocols; Prototypes; Real time systems; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2008 IEEE International
Conference_Location
Newport Beach, CA
Print_ISBN
978-1-4244-2596-9
Electronic_ISBN
978-1-4244-2597-6
Type
conf
DOI
10.1109/SOCC.2008.4641485
Filename
4641485
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