Exact probabilistic analysis of error detection for parity checkers

Error detection probability and latency of the parity checker with respect to single stuck-at faults in the circuit under check (CUC) are calculated analytically. A notion of “multi-output supergate” is introduced for multi-output combinational CUC generalizing the formerly known notion of (single-output) supergate. “Restricted” observabilities and detectabilities are calculated for each line in the CUC with respect to non-empty subsets of outputs of the CUC. The method may be easily extended for other concurrent checkers as well