OFDM symbol timing synchronization system on a Reconfigurable Instruction Cell Array

In this paper, we present a flexible and compact OFDM symbol timing synchronization system targeting a dynamically reconfigurable instruction cell array (RICA). The system is based on the cyclic prefix and maximum likelihood (ML) estimation algorithm. Pure ANSI-C programmability and custom tailored cells make this synchronization system flexible and have low energy consumption. Various approaches have been utilized for the algorithmic simplification and optimization in both hardware and software. The synchronization system provides a high throughput of 81.6 Msample/s working with a clock rate of 51 MHz, and occupying 1.4 mm² cell area based on a 0.18 micron technology. Power consumption is calculated to be 17 mW when working at the rate of 25.3 Msample/s.