A novel methodology for hardware acceleration and emulation

The communication overhead between the software emulator in the workstation and the FPGA emulator is the speed bottleneck of the hardware acceleration platform. This paper presents a vector mode based hardware/software co-emulation methodology, which leverages the pipeline structure to transmit, receive and buffer data. This methodology reduces the communication overhead by carrying out a parallel mechanism in that while user´s design is under test in the emulator, signal data are transmitting in the channel simultaneously, thus increasing the speed of hardware acceleration and emulation. The results of two experiments show that the acceleration factor is 747 and 157, respectively, compared with the traditional methodology.