• DocumentCode
    3045106
  • Title

    Dynamically reconfigurable neuron architecture for the implementation of self- organizing learning array

  • Author

    Starzyk, Janusz A. ; Guo, Yongtao ; Zhu, Zhineng

  • Author_Institution
    Sch. of Electr. Eng. & Comput. Sci., Ohio Univ., Athens, OH, USA
  • fYear
    2004
  • fDate
    26-30 April 2004
  • Firstpage
    143
  • Abstract
    Summary form only given. We describe a new dynamically reconfigurable neuron hardware architecture based on the modified Xilinx Picoblaze microcontroller and self-organizing learning array (SOLAR) algorithm reported earlier. This architecture is aiming at using hundreds of traditional reconfigurable field programmable gate arrays (FPGAs) to build the SOLAR learning machine. SOLAR has many advantages over traditional neural network hardware implementation. Neurons are optimized for area and speed, and the whole system is dynamically self-reconfigurable during the runtime. The system architecture is expandable to a large multiple-chip system.
  • Keywords
    field programmable gate arrays; microcontrollers; neural chips; neural net architecture; reconfigurable architectures; self-organising feature maps; FPGA; Xilinx Picoblaze microcontroller; neural network hardware implementation; reconfigurable field programmable gate array; reconfigurable neuron hardware architecture; self-organizing learning array algorithm; Artificial neural networks; Biology computing; Computer architecture; Field programmable gate arrays; Machine learning; Machine learning algorithms; Neural network hardware; Neurons; Runtime; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International
  • Print_ISBN
    0-7695-2132-0
  • Type

    conf

  • DOI
    10.1109/IPDPS.2004.1303122
  • Filename
    1303122