An 8-MHz bandwidth continuous-time ΔΣ modulator with DAC error sensitivity reduction for medical ultrasonic applications

This paper proposed a new architecture to mitigate digital-to-analog converter (DAC) errors in a continuous-time ΔΣ modulator (CTSDM). The modulator adopted the 3^rd-order loop filter with dual-loop architecture. Digital integrator feedback (DIF) technique is proposed to tolerate more clock jitter and DAC errors. Multi-bit quantizer and non-return-to-zero (NRZ) DAC are utilized to reduce clock jitter sensitivity. The proposed design effectively addresses the noise introduced by the multi-bit DAC with the assistance of a simple digital first-order digital filter. The presented CTSDM achieves 79dB SNR, and 82dB dynamic range. This design is implemented in a TSMC 0.18μm CMOS process. The power consumption is only 2.5mW. Low power and wide bandwidth make this ADC suitable for portable medical ultrasonic applications.