Test synthesis for DC test and maximal diagnosis of switched-capacitor circuits

This paper presents a DFT/BIST technique for switched-capacitor (SC) circuits that consists of measuring all capacitance ratios of transfer functions in the DC domain. Then, the specifications of a SC circuit are computed from these measured capacitance ratios and compared to the fault-free ones. Moreover a maximal fault diagnosis is realized for the capacitances. This test technique uses re-configurations of the circuit so as that all the capacitance ratios are measured one by one at the different operational amplifiers outputs of the circuit. For this purpose, a standardized re-configuration of the three capacitances types, switched, un-switched and integrating capacitances, is described. Then, a test synthesis algorithm based on the fluency graph description of SC circuits is proposed and offers a formal approach to automate the technique. Finally, some recommendations concerning the design of the extra switches are given and simulations prove the low performance degradation of the circuit in test mode