A 1.3µW 0.0075mm2 neural amplifier and capacitor-integrated electrodes for high density neural implant recording

A key issue in the design of biomedical implants is the design of low-power area-efficient circuits that allow for high-density neural recording. This paper presents an ultra low-power (<;1.4μW), area efficient low-noise neural amplifier that utilizes current-feedback miller-compensation technique and occupies ~ 0.0075mm² silicon area. Integrating the large input capacitor within the electrodes saves valuable silicon area. The amplified signal is digitized by a 10-bit sigma-delta ADC that is based on an area-efficient self-biased amplifier. The ADC consumes only 4.8μW from a 1.2V supply, when sampled with a 1.6MHz, and occupies 0.03mm² chip area. The chip was fabricated in 0.13μm CMOS.