Synthesis of parallel hierarchical finite state machines

Author

Sklyarov, Valery ; Skliarova, Iouliia

Author_Institution

Dept. of Electron., Telecommun. & Inf., Univ. of Aveiro, Aveiro, Portugal

fYear

2013

fDate

14-16 May 2013

Firstpage

1

Lastpage

8

Abstract

This paper presents a novel model and method for synthesis of parallel hierarchical finite state machines (PHFSM) that permit to implement such algorithms, which are: 1) composed of modules; 2) the modules can be activated from other modules; 3) more than one module can be activated in parallel. The synthesis involves three basic steps: 1) conversion of a given specification to special state transition diagrams; 2) use of the proposed hardware description language templates; 3) synthesis of the circuit from the templates. The results of experiments have proven the effectiveness and practicability of the proposed technique.

Keywords

finite state machines; hardware description languages; logic design; parallel architectures; PHFSM synthesis method; circuit synthesis; hardware description language; parallel hierarchical finite state machine synthesis; state transition diagrams; Application specific integrated circuits; Automata; Clocks; Field programmable gate arrays; Hardware; Integrated circuit modeling; Synchronization; Hierarchy; hardware accelerators; programming techniques; recursion;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2013 21st Iranian Conference on

Conference_Location

Mashhad

Type

conf

DOI

10.1109/IranianCEE.2013.6599683

Filename

6599683