DocumentCode :
3050199
Title :
Logarithmic delay for N×N packet switches
Author :
Neely, Michael J. ; Modiano, Eytan
fYear :
2004
fDate :
2004
Firstpage :
3
Lastpage :
9
Abstract :
We consider the fundamental delay bounds for scheduling packets in an N×N packet switch operating under the crossbar constraint. Algorithms that make scheduling decisions without considering queue backlog are shown to incur an average delay of at least O(N). We then prove that O(log(N)) delay is achievable with a simple frame based algorithm that uses queue backlog information. This is the best known delay bound for packet switches, and is the first analytical proof that sublinear delay is achievable in a packet switch with random inputs. The algorithm is shown to be implementable with very low complexity, requiring O(N1.5 log(N)) total operations per timeslot.
Keywords :
computational complexity; delays; packet switching; queueing theory; scheduling; complexity; crossbar constraint; frame based algorithm; logarithmic delay; packet scheduling; packet switches; queue backlog; Constraint theory; Delay; Fabrics; Optimal control; Packet switching; Processor scheduling; Queueing analysis; Scheduling algorithm; Switches; World Wide Web;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Switching and Routing, 2004. HPSR. 2004 Workshop on
Print_ISBN :
0-7803-8375-3
Type :
conf
DOI :
10.1109/HPSR.2004.1303412
Filename :
1303412
Link To Document :
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